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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Container structure for descriptor storage control.  <a href="struct_x_axi_dma___bd_ring.html#details">More...</a><br/></td></tr>
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Macros</h2></td></tr>
<tr class="memitem:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga5c87fcb74fe669b5998e53d0a4b35127">XAxiDma_BdRingCntCalc</a>(Alignment, Bytes)&#160;&#160;&#160;(uint32_t)((Bytes)/((sizeof(<a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1))&amp;~((Alignment)-1)))</td></tr>
<tr class="memdesc:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use this macro at initialization time to determine how many BDs will fit within the given memory constraints.  <a href="group___a_x_i_d_m_a.html#ga5c87fcb74fe669b5998e53d0a4b35127">More...</a><br/></td></tr>
<tr class="separator:ga5c87fcb74fe669b5998e53d0a4b35127"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6899085c400b8f453381b305ac5521d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga6899085c400b8f453381b305ac5521d9">XAxiDma_BdRingMemCalc</a>(Alignment, NumBd)&#160;&#160;&#160;(int)((sizeof(<a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a>)+((Alignment)-1)) &amp; ~((Alignment)-1))*(NumBd)</td></tr>
<tr class="memdesc:ga6899085c400b8f453381b305ac5521d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Use this macro at initialization time to determine how many bytes of memory are required to contain a given number of BDs at a given alignment.  <a href="group___a_x_i_d_m_a.html#ga6899085c400b8f453381b305ac5521d9">More...</a><br/></td></tr>
<tr class="separator:ga6899085c400b8f453381b305ac5521d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac62389e25e6775026cf1be6c383e665b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gac62389e25e6775026cf1be6c383e665b">XAxiDma_BdRingGetCnt</a>(RingPtr)&#160;&#160;&#160;((RingPtr)-&gt;AllCnt)</td></tr>
<tr class="memdesc:gac62389e25e6775026cf1be6c383e665b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the total number of BDs allocated by this channel with <a class="el" href="group___a_x_i_d_m_a.html#ga5c6d6f492642dd355478c3a853556d6b" title="Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring...">XAxiDma_BdRingCreate()</a>.  <a href="group___a_x_i_d_m_a.html#gac62389e25e6775026cf1be6c383e665b">More...</a><br/></td></tr>
<tr class="separator:gac62389e25e6775026cf1be6c383e665b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga415cf0c379fef0104f9f52881ead13a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga415cf0c379fef0104f9f52881ead13a7">XAxiDma_BdRingGetFreeCnt</a>(RingPtr)&#160;&#160;&#160;((RingPtr)-&gt;FreeCnt)</td></tr>
<tr class="memdesc:ga415cf0c379fef0104f9f52881ead13a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the number of BDs allocatable with <a class="el" href="group___a_x_i_d_m_a.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> for pre- processing.  <a href="group___a_x_i_d_m_a.html#ga415cf0c379fef0104f9f52881ead13a7">More...</a><br/></td></tr>
<tr class="separator:ga415cf0c379fef0104f9f52881ead13a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0d79253861939c76e6d440ecde2b6edd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga0d79253861939c76e6d440ecde2b6edd">XAxiDma_BdRingSnapShotCurrBd</a>(RingPtr)</td></tr>
<tr class="memdesc:ga0d79253861939c76e6d440ecde2b6edd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Snap shot the latest BD a BD ring is processing.  <a href="group___a_x_i_d_m_a.html#ga0d79253861939c76e6d440ecde2b6edd">More...</a><br/></td></tr>
<tr class="separator:ga0d79253861939c76e6d440ecde2b6edd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd32e45591597a4bfa84b66dffc98913"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gadd32e45591597a4bfa84b66dffc98913">XAxiDma_BdRingGetCurrBd</a>(RingPtr)</td></tr>
<tr class="memdesc:gadd32e45591597a4bfa84b66dffc98913"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the BD a BD ring is processing.  <a href="group___a_x_i_d_m_a.html#gadd32e45591597a4bfa84b66dffc98913">More...</a><br/></td></tr>
<tr class="separator:gadd32e45591597a4bfa84b66dffc98913"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga4b7e75d1acf86428bd79fcd0d1c13745">XAxiDma_BdRingNext</a>(RingPtr, BdPtr)</td></tr>
<tr class="memdesc:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the next BD in the ring.  <a href="group___a_x_i_d_m_a.html#ga4b7e75d1acf86428bd79fcd0d1c13745">More...</a><br/></td></tr>
<tr class="separator:ga4b7e75d1acf86428bd79fcd0d1c13745"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga86c6d4b9c4f8766634d46a3078eadc8a">XAxiDma_BdRingPrev</a>(RingPtr, BdPtr)</td></tr>
<tr class="memdesc:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Return the previous BD in the ring.  <a href="group___a_x_i_d_m_a.html#ga86c6d4b9c4f8766634d46a3078eadc8a">More...</a><br/></td></tr>
<tr class="separator:ga86c6d4b9c4f8766634d46a3078eadc8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga740fa349c7811de2b7bae5cf83eb445e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga740fa349c7811de2b7bae5cf83eb445e">XAxiDma_BdRingGetSr</a>(RingPtr)&#160;&#160;&#160;<a class="el" href="group___a_x_i_d_m_a.html#gadea426ef26fc5473a78723cd2b92aba5">XAxiDma_ReadReg</a>((RingPtr)-&gt;ChanBase, <a class="el" href="group___a_x_i_d_m_a.html#ga50d6957f8447d4eab9e444666730f692">XAXIDMA_SR_OFFSET</a>)</td></tr>
<tr class="memdesc:ga740fa349c7811de2b7bae5cf83eb445e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the contents of the channel status register.  <a href="group___a_x_i_d_m_a.html#ga740fa349c7811de2b7bae5cf83eb445e">More...</a><br/></td></tr>
<tr class="separator:ga740fa349c7811de2b7bae5cf83eb445e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">XAxiDma_BdRingGetError</a>(RingPtr)</td></tr>
<tr class="memdesc:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get error bits of a DMA channel.  <a href="group___a_x_i_d_m_a.html#ga24cd47cdbfac0813e0d9caf966a1a3d2">More...</a><br/></td></tr>
<tr class="separator:ga24cd47cdbfac0813e0d9caf966a1a3d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga766bed2454969636d827fb79faeeee97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga766bed2454969636d827fb79faeeee97">XAxiDma_BdRingHwIsStarted</a>(RingPtr)</td></tr>
<tr class="memdesc:ga766bed2454969636d827fb79faeeee97"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check whether a DMA channel is started, meaning the channel is not halted.  <a href="group___a_x_i_d_m_a.html#ga766bed2454969636d827fb79faeeee97">More...</a><br/></td></tr>
<tr class="separator:ga766bed2454969636d827fb79faeeee97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaf7c291190c92ce93d72f95c5b04ef1d4">XAxiDma_BdRingBusy</a>(RingPtr)</td></tr>
<tr class="memdesc:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check if the current DMA channel is busy with a DMA operation.  <a href="group___a_x_i_d_m_a.html#gaf7c291190c92ce93d72f95c5b04ef1d4">More...</a><br/></td></tr>
<tr class="separator:gaf7c291190c92ce93d72f95c5b04ef1d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2518030938ab80081f6896fc5589682c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga2518030938ab80081f6896fc5589682c">XAxiDma_BdRingIntEnable</a>(RingPtr, Mask)</td></tr>
<tr class="memdesc:ga2518030938ab80081f6896fc5589682c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt enable bits for a channel.  <a href="group___a_x_i_d_m_a.html#ga2518030938ab80081f6896fc5589682c">More...</a><br/></td></tr>
<tr class="separator:ga2518030938ab80081f6896fc5589682c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gadbb17169213d8af8b50e6dee7f7b6d8b">XAxiDma_BdRingIntGetEnabled</a>(RingPtr)</td></tr>
<tr class="memdesc:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get enabled interrupts of a channel.  <a href="group___a_x_i_d_m_a.html#gadbb17169213d8af8b50e6dee7f7b6d8b">More...</a><br/></td></tr>
<tr class="separator:gadbb17169213d8af8b50e6dee7f7b6d8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0269e07693c731cf7721c6f19f8eb69b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga0269e07693c731cf7721c6f19f8eb69b">XAxiDma_BdRingIntDisable</a>(RingPtr, Mask)</td></tr>
<tr class="memdesc:ga0269e07693c731cf7721c6f19f8eb69b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear interrupt enable bits for a channel.  <a href="group___a_x_i_d_m_a.html#ga0269e07693c731cf7721c6f19f8eb69b">More...</a><br/></td></tr>
<tr class="separator:ga0269e07693c731cf7721c6f19f8eb69b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga7a9d2103e6d09fc3850b34a6386dc803">XAxiDma_BdRingGetIrq</a>(RingPtr)</td></tr>
<tr class="memdesc:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve the contents of the channel's IRQ register XAXIDMA_SR_OFFSET.  <a href="group___a_x_i_d_m_a.html#ga7a9d2103e6d09fc3850b34a6386dc803">More...</a><br/></td></tr>
<tr class="separator:ga7a9d2103e6d09fc3850b34a6386dc803"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9e782e3715c1d2dd03e5d03434f47319"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga9e782e3715c1d2dd03e5d03434f47319">XAxiDma_BdRingAckIrq</a>(RingPtr, Mask)</td></tr>
<tr class="memdesc:ga9e782e3715c1d2dd03e5d03434f47319"><td class="mdescLeft">&#160;</td><td class="mdescRight">Acknowledge asserted interrupts.  <a href="group___a_x_i_d_m_a.html#ga9e782e3715c1d2dd03e5d03434f47319">More...</a><br/></td></tr>
<tr class="separator:ga9e782e3715c1d2dd03e5d03434f47319"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa44d5f8239080614bb5c180c169e2334"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaa44d5f8239080614bb5c180c169e2334">XAxiDma_BdRingEnableCyclicDMA</a>(RingPtr)&#160;&#160;&#160;(RingPtr-&gt;Cyclic = 1)</td></tr>
<tr class="memdesc:gaa44d5f8239080614bb5c180c169e2334"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable Cyclic DMA Mode.  <a href="group___a_x_i_d_m_a.html#gaa44d5f8239080614bb5c180c169e2334">More...</a><br/></td></tr>
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Functions</h2></td></tr>
<tr class="memitem:ga7b38bc9220c391823219937580bd816f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga7b38bc9220c391823219937580bd816f">XAxiDma_StartBdRingHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga7b38bc9220c391823219937580bd816f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA channel and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.  <a href="group___a_x_i_d_m_a.html#ga7b38bc9220c391823219937580bd816f">More...</a><br/></td></tr>
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<tr class="memitem:ga39ee7d89e4453276d615849acad27fde"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga39ee7d89e4453276d615849acad27fde">XAxiDma_UpdateBdRingCDesc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga39ee7d89e4453276d615849acad27fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">Update Current Descriptor.  <a href="group___a_x_i_d_m_a.html#ga39ee7d89e4453276d615849acad27fde">More...</a><br/></td></tr>
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<tr class="memitem:ga5c6d6f492642dd355478c3a853556d6b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga5c6d6f492642dd355478c3a853556d6b">XAxiDma_BdRingCreate</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, UINTPTR PhysAddr, UINTPTR VirtAddr, u32 Alignment, int BdCount)</td></tr>
<tr class="memdesc:ga5c6d6f492642dd355478c3a853556d6b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Using a memory segment allocated by the caller, This fundtion creates and setup the BD ring.  <a href="group___a_x_i_d_m_a.html#ga5c6d6f492642dd355478c3a853556d6b">More...</a><br/></td></tr>
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<tr class="memitem:gad044df5bd676a71226411ba7f78ef20b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gad044df5bd676a71226411ba7f78ef20b">XAxiDma_BdRingClone</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *SrcBdPtr)</td></tr>
<tr class="memdesc:gad044df5bd676a71226411ba7f78ef20b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clone the given BD into every BD in the ring.  <a href="group___a_x_i_d_m_a.html#gad044df5bd676a71226411ba7f78ef20b">More...</a><br/></td></tr>
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<tr class="memitem:ga44003cd704b7d4868d1dc00bb433a91f"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga44003cd704b7d4868d1dc00bb433a91f">XAxiDma_BdRingAlloc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **BdSetPtr)</td></tr>
<tr class="memdesc:ga44003cd704b7d4868d1dc00bb433a91f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserve locations in the BD ring.  <a href="group___a_x_i_d_m_a.html#ga44003cd704b7d4868d1dc00bb433a91f">More...</a><br/></td></tr>
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<tr class="memitem:gac58b1ab7a89890142baf67211772d3ce"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gac58b1ab7a89890142baf67211772d3ce">XAxiDma_BdRingUnAlloc</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gac58b1ab7a89890142baf67211772d3ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fully or partially undo an <a class="el" href="group___a_x_i_d_m_a.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a> operation.  <a href="group___a_x_i_d_m_a.html#gac58b1ab7a89890142baf67211772d3ce">More...</a><br/></td></tr>
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<tr class="memitem:gaac81111b373e373be7dd3989fffffe7b"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaac81111b373e373be7dd3989fffffe7b">XAxiDma_BdRingToHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gaac81111b373e373be7dd3989fffffe7b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enqueue a set of BDs to hardware that were previously allocated by <a class="el" href="group___a_x_i_d_m_a.html#ga44003cd704b7d4868d1dc00bb433a91f" title="Reserve locations in the BD ring. ">XAxiDma_BdRingAlloc()</a>.  <a href="group___a_x_i_d_m_a.html#gaac81111b373e373be7dd3989fffffe7b">More...</a><br/></td></tr>
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<tr class="memitem:ga1e5d328b4d4a247d1530fac3efe4c59c"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga1e5d328b4d4a247d1530fac3efe4c59c">XAxiDma_BdRingFromHw</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int BdLimit, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> **BdSetPtr)</td></tr>
<tr class="memdesc:ga1e5d328b4d4a247d1530fac3efe4c59c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns a set of BD(s) that have been processed by hardware.  <a href="group___a_x_i_d_m_a.html#ga1e5d328b4d4a247d1530fac3efe4c59c">More...</a><br/></td></tr>
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<tr class="memitem:gad2ac76e5a39486896cd484e51d2898c7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gad2ac76e5a39486896cd484e51d2898c7">XAxiDma_BdRingFree</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, int NumBd, <a class="el" href="group___a_x_i_d_m_a.html#ga5faf4d844b10fc577f3a75a170f11867">XAxiDma_Bd</a> *BdSetPtr)</td></tr>
<tr class="memdesc:gad2ac76e5a39486896cd484e51d2898c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frees a set of BDs that had been previously retrieved with <a class="el" href="group___a_x_i_d_m_a.html#ga1e5d328b4d4a247d1530fac3efe4c59c" title="Returns a set of BD(s) that have been processed by hardware. ">XAxiDma_BdRingFromHw()</a>.  <a href="group___a_x_i_d_m_a.html#gad2ac76e5a39486896cd484e51d2898c7">More...</a><br/></td></tr>
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<tr class="memitem:gaafd18a1df185c30b4745c147e3295ac3"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaafd18a1df185c30b4745c147e3295ac3">XAxiDma_BdRingStart</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:gaafd18a1df185c30b4745c147e3295ac3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start a DMA channel, updates current descriptors and Allow DMA transactions to commence on a given channel if descriptors are ready to be processed.  <a href="group___a_x_i_d_m_a.html#gaafd18a1df185c30b4745c147e3295ac3">More...</a><br/></td></tr>
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<tr class="memitem:gaaebba5c661e04485582e887e74dbeb94"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaaebba5c661e04485582e887e74dbeb94">XAxiDma_BdRingSetCoalesce</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, u32 Counter, u32 Timer)</td></tr>
<tr class="memdesc:gaaebba5c661e04485582e887e74dbeb94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set interrupt coalescing parameters for the given descriptor ring channel.  <a href="group___a_x_i_d_m_a.html#gaaebba5c661e04485582e887e74dbeb94">More...</a><br/></td></tr>
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<tr class="memitem:ga0d3794bbccf028da8e94407d061dfc68"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga0d3794bbccf028da8e94407d061dfc68">XAxiDma_BdRingGetCoalesce</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr, u32 *CounterPtr, u32 *TimerPtr)</td></tr>
<tr class="memdesc:ga0d3794bbccf028da8e94407d061dfc68"><td class="mdescLeft">&#160;</td><td class="mdescRight">Retrieve current interrupt coalescing parameters from the given descriptor ring channel.  <a href="group___a_x_i_d_m_a.html#ga0d3794bbccf028da8e94407d061dfc68">More...</a><br/></td></tr>
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<tr class="memitem:ga64cf3c732bc803da742c256ab6372e0e"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#ga64cf3c732bc803da742c256ab6372e0e">XAxiDma_BdRingCheck</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:ga64cf3c732bc803da742c256ab6372e0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Check the internal data structures of the BD ring for the provided channel.  <a href="group___a_x_i_d_m_a.html#ga64cf3c732bc803da742c256ab6372e0e">More...</a><br/></td></tr>
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<tr class="memitem:gaffa661a9a2467c1e274842c147531cea"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group___a_x_i_d_m_a.html#gaffa661a9a2467c1e274842c147531cea">XAxiDma_BdRingDumpRegs</a> (<a class="el" href="struct_x_axi_dma___bd_ring.html">XAxiDma_BdRing</a> *RingPtr)</td></tr>
<tr class="memdesc:gaffa661a9a2467c1e274842c147531cea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Dump the registers for a channel.  <a href="group___a_x_i_d_m_a.html#gaffa661a9a2467c1e274842c147531cea">More...</a><br/></td></tr>
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